FIG. 1 illustrates a single phase prior art converter employing what is known as "bang bang" control. The inverter 10 produces an AC voltage which varies sinusoidally at a fundamental frequency which is applied to a load 12. The magnitude of the output voltage is controlled by a voltage reference V.sub.REF which is proportional to a desired regulated output voltage to be outputted by the inverter to the load 12. The inverter 10 has a voltage control loop 14 which produces an error voltage outputted by summer 16 which is proportional to the difference between the output voltage produced by the inverter and the reference voltage V.sub.REF. The output voltage is converted from AC to a DC signal by a signal processing circuit 18 which rectifies the AC voltage and low pass filters the rectified voltage for application to the subtracting input of the summer 16. The error signal produced by the summer 16 is applied to error amplifier 20 which may be a PI controller. The amplified error voltage VE produced by error amplifier 20 is multiplied by multiplier 22 with a reference current signal sin .cndot.t which varies at the fundamental frequency. Reference signal generator 24, which is comprised of an adder 26, subtractor 28 and DC bias source 30, produces an upper level current signal on input 32 of a window comparator 36 and a lower level current signal on input 34 of the window comparator. The DC bias source 30 produces a fixed level DC bias which is applied to an input of the adder 26 and subtractor 28. The upper level current signal on the input 32 of the window comparator 36 is equal to the sum of the constant DC bias produced by the DC bias source 30 and the output of the multiplier 22. The window comparator 36 changes state each time the current sensed by current sensor 38 matches either of the upper or lower current limit signals inputted on the inputs 32 and 34 of the window comparator 36. The output pulses produced by the window comparator 36 are applied to a signal generator 44 which produces bistable output signals on outputs Q and Q. The signal generator 44 is a bistable circuit which provides a short zero voltage output level on both of the outputs Q and -Q- in response to an output signal from the window comparator 36 to ensure that shoot-thru does not exist in the transistor switches Q1 and Q2 of the inverter. Freewheeling diodes 46 and snubbing capacitors 48 are connected in parallel with the transistor switches Q1 and Q2 in a conventional fashion. DC power sources 50 supply current which flows through the load 12 in response to turning on of the transistors Q1 and Q2 in conventional fashion. While the inverter is illustrated as a half bridge inverter having two switches, "bang bang" control has also been used for full bridge inverters having four switches.
Current flow through the inductor 42 varies cyclically at a corner frequency higher than the fundamental frequency of the AC voltage outfitted by filter 40. The corner frequency is determined by the inductor and capacitor values of the filter 42 and the spacing between the upper current level signal on input 32 and the lower current level signal on input 34. The envelope of the cyclical current flow defines the fundamental output frequency of the AC produced by the inverter.
The inverter of FIG. 1 has the disadvantage that the switching of the transistors Q1 and Q2 into conduction does not occur only when the freewheeling diodes 46 are conductive. A paper entitled "A Control Strategy for Reference Wave Adaptive Current Generation" authored by R. Palaniappann and J. Vithayathil, IEEE Transactions on Industrial Electronics and Control Instrumentation, Vol. IECI-27, No. 2, May 1980 illustrates in FIG. 1 the upper and lower current level signals like those produced by the adders 26 and 28. The upper and lower current level signals which are respectively applied to inerts 32 and 34 of the window comparator 36 as illustrated in FIG. 1 of the aforementioned publication are not respectively disposed on the positive and negative sides of the zero current flow. As a result the signal generator 44 will turn on one of the transistors Q1 and Q2 when the parallel connected freewheeling diode 46 is not conductive resulting in the transistor being turned on with its parallel connected freewheeling diode not conductive being subjected to increased stress as a result of switching the power supply potential by the transistor and further consuming additional power over that which would be consumed if the transistor is switched on while the freewheeling diode 46 is conductive which clamps the potential across the transistor being switched on to one diode drop.